The present invention relates generally to integrated circuit (IC) designs, and more particularly to a voltage-controlled oscillator (VCO) of a phase-locked loop (PLL) circuit that provides gain compensation for the SS corner in order to improve the phase margin degradation and to improve the circuit area.
PLL circuits are commonly used to generate a high-frequency signal with a frequency being an accurate multiple of the frequency of a reference signal. PLL circuits can also be found in applications where the phase of the output signal has to track the phase of the reference signal, hence the name phase-locked loop. The VCO circuit is the key component used in the PLL circuit.
The VCO circuits generate output frequencies over a wide range in response to a small change in input control voltage, Vc. The ratio of a change in the output oscillator frequency to a change in the input control voltage Vc is known as the VCO gain or Kvco. The gain of a VCO is a factor in the PLL's open loop gain, and therefore can have an effect on the PLL's overall stability.
In simulation, the best-case signal ringing (referred to as an FF corner) and worst-case signal delay (referred to as an SS corner) for VCO circuits are determined. The initials FF and SS refer to the characteristics of the p and n channel transistors, respectively. An FF VCO simulation refers to fast p-channel and n-channel transistors. An SS VCO simulation means that both p-channel and n-channel transistors are slow during the simulation.
For a low voltage VCO design, the Kvco degrades or the frequency saturates at higher voltages for SS corner simulation. To meet the minimum requirement of oscillation frequency for the SS corner, Kvco has to be increased. However, increasing Kvco of the SS corner also increases the Kvco of the FF corner. The stability of the PLL circuit depends on the loop bandwidth and is directly proportional to Kvco. Increasing Kvco of the FF corner causes the capacitance area to increase in order to maintain stability. Due to the frequency saturation of the SS corner, the gain of diversity from the SS corner to the FF corner increases, resulting in phase margin degradation.
As such, it is desirable to have a VOC design with gain compensation that improves the phase margin and reduces the capacitance area.